The PCI Special Interest Group (PCI SIG) has published the first official draft of the PCIe Gen 7.0 specification, which includes all changes to the Gen 7 specification compared to PCI Gen 6.<\/p>\n\n\n\n
Gen 7 is the next revision of PCI Express after Gen 6. If you thought Gen 6 was already very fast, Gen 7 will double the bandwidth of Gen 6, allowing data transfer speeds of up to 128 GT\/s. This means that a PCIe Gen 7 x16 slot can bi-directionally transfer as much as 512 GB\/s from the processor to a Gen 7-capable add-in card and vice versa.<\/p>\n\n\n\n
Although Gen 7 has greatly increased bandwidth over its predecessor, it uses some features that Gen 6 already uses today, including PAM4 signaling and flit 1b\/1b mode encoding. This makes Gen 7's architectural design strikingly similar to Gen 6, which could accelerate adoption by manufacturers already experienced with Gen 6 deployments.<\/p>\n\n\n\n
The transition from PCIe 4.0 to 5.0 doubled the data transfer rate by increasing the bus frequency, which introduced new limitations such as roughly halving the trace length. This meant that devices had to be placed closer together to maintain signal integrity, and there were demands for thicker baseplates and more robust materials.<\/p>\n\n\n\n
The new PCIe 6.0 interface doubles the throughput again, but this is increased by switching to PAM-4 encoding from NRZ instead of increasing the frequency, so the range\/distance requirements remain roughly the same. However, PAM-4 encoding is more error-sensitive, so the error rate increased despite the addition of forward error correction (FEC). While the bandwidth has doubled, the error rate has also increased, reducing the effective bandwidth.<\/p>\n\n\n\n
We won't see PCIe Gen 7 for a long time, not even after the 2025 debut. These cutting-edge technologies usually take several years before they become widely available to consumers. At first, we will only see them in companies or server environments.<\/p>\n