Huawei announces hunt for 1.4-nanometer process with new “stacking” technology

Huawei still lags behind the world's leading manufacturers in processor production, such as TSMC, Samsung Foundry and Intel. Although this technological gap will remain noticeable for some time, the situation is expected to change soon. Huawei has officially announced an ambitious long-term plan, according to which it intends to directly compete with TSMC's advanced 1.4nm manufacturing process by 2031. Although the company will still be about a generation behind at that time, this level of integration should be more than enough to keep the Chinese technology ecosystem fully competitive with Western competitors.

To achieve this breakthrough, Huawei plans to use a technology it calls “logic stacking.” It is an upgrade to existing three-dimensional stacking methods, in which two chips are placed directly on top of each other. This process achieves a significantly higher density of transistors on the same area of a silicon wafer without requiring finer patterning. The latter requires advanced EUV (extreme ultraviolet lithography) tools, to which China does not currently have access. According to official statements, the next generation of Kirin 2026 processors will be among the first commercially available chips to take advantage of this approach.

Despite the current restrictions, China has reportedly built a partially functional EUV machine with the help of former ASML engineers. The device is not yet ready for production, but is expected to be fully functional by 2031. Combined with Huawei's existing efforts to break the 2nm barrier with techniques such as SAQP (self-aligned quadruple patterning), this should allow Huawei and SMIC to successfully overcome the 5nm barrier and produce even denser silicon.

Interestingly, Huawei didn't address the key issue with this type of design during the presentation, namely cooling. Stacking multiple chips vertically on top of each other will generate significantly more heat than conventional single-layer designs.